This invention relates to a technique for manufacturing a semiconductor integrated circuit device; and, more particularly, the invention relates to a technique that may be effectively used to form an insulating film on a metal wiring.
Recently, a technique for making a laminated structure, formed of an element and wiring, has been developed concomitantly with high integration of an LSI. Though elements in such a structure are separated by an interlayer insulating film which is disposed therebetween, the problem of separation or breakage of the wiring due to the film stress of the conductive layer or interlayer insulating film, which constitutes an element or wiring of the laminate, has been revealed as the lamination has been developed.
More particularly, in the case where the process involves high temperature heat treatment after the interlayer insulating film is formed on the top of wiring, it has been found that such heat treatment causes an increased film stress and results in the problem of wiring separation or breakage.
For example, Japanese Published Unexamined Patent Application No. Hei 10(1998)-173049 discloses a technique in which a BPSG (Boro-Phosphate-silicate glass) film 83 is coated on the surface of a bit-line wiring layer by means of a CVD (Chemical Vapor Deposition) technique. Furthermore, this published patent application discloses a technique which involves the use of a HDP-SiO (High Density Plasma Silicon Oxide) film instead of a BPSG film, which allows the high temperature treatment in the forming process to be eliminated, whereby the thermal stress can be suppressed extremely.
Furthermore, Japanese Published Unexamined Patent Application No. Hei 11(1999)-243180 discloses a technique in which a third interlayer insulating film, that serves to insulate between a bit-line 27 and a bottom electrode of a capacitor, is formed as a silicon oxide film by use of a plasma CVD technique, wherein a special film forming condition is employed.
The inventors of the present invention have developed various techniques to improve the performance of a semiconductor integrated circuit device, including techniques to solve the above-mentioned problem of wiring separation and breakage.
For example, a memory cell of a DRAM (Dynamic Random Access Memory) comprises a memory cell selection MISFET (Metal Insulator Semiconductor Field Effect Transistor) and a capacitor (information storing capacitor element) that is connected in series to the memory cell selection MISFET, and a terminal thereof that is not connected to the capacitor is connected to a bit-line.
In the case of a so-called COB (capacitor over bit-line) structure, among the various known DRAM structures, a capacitor is formed on the top of a bit-line and an interlayer insulating film is formed between the bit-line and the capacitor, as will be described hereinafter. As described hereinafter, the capacitor forming process includes a high temperature heat treatment step, so that breaking and separation of a bit-line can be caused due to the difference in film stress between the bit-line and the interlayer insulating film.
It is an object of the present invention to relax the film stress of the wiring and an insulating film formed on the top thereof, that form structural components of a semiconductor integrated circuit device, and to prevent the breakage or separation of the wiring.
Furthermore, another object of the present invention is to improve the performance of a semiconductor integrated circuit device.
The above-mentioned objects, other objects, and novel features of the present invention will be apparent from the following description of the present invention and the attached drawings.
An outline of representative aspects and features of the present invention, as disclosed in the present application, will be described briefly hereinafter.
(1) A method of manufacture of a semiconductor integrated circuit device in accordance with the present invention involves a successive process in which a second insulating film is formed at a first temperature so as to cover wiring, the second insulating film is subjected to heat treatment at a second temperature that is higher than the first temperature, and then a first electrode, a dielectric film and a second electrode are formed on the second insulating film.
(2) A method of manufacture of a semiconductor integrated circuit device in accordance with the present invention comprises the steps of forming a second insulating film so as to cover wiring by means of a chemical vapor deposition technique, forming a third insulating film, which is a coated film, on the second insulating film, and, after heat-treating at a first temperature, forming a fourth insulating film on the third insulating film by means of a chemical vapor deposition technique, and further forming a first electrode, a dielectric film and a second electrode on the fourth insulating film, wherein the step of forming the dielectric film includes a step of heat-treating the dielectric film at a second temperature, wherein the first temperature is equal to or higher than the second temperature.
(3) A method of manufacture of a semiconductor integrated circuit device in accordance with the present invention comprises the steps of forming a second insulating film so as to cover wiring, heat-treating the second insulating film at a first temperature, thereafter etching the second insulating film so that the surface of the wiring is exposed to form an aperture on the second insulating film, forming a first conductive layer inside the aperture at a second temperature by means of a chemical vapor deposition technique, forming a second conductive layer on the first conductive layer, and polishing the first and second conductive layers so that the first and second conductive layers remain selectively inside the aperture, wherein the first temperature is equal to or higher than the second temperature.